1. Field of the Invention
The present invention relates to a method for recovering a clock signal from an input data signal in a telecommunications system.
2. Description of the Prior Art
When establishing digital communication systems, often the condition arises where a local oscillator generates the frequency for sending data to a remote receiver terminal, which by extracting clock information from the data themselves, e.g. through a PLL circuit (Phase Locked Loop), uses such a frequency to read the data received and clock its own transmission.
FIG. 1a is representing by way of example a basic diagram of a synchronous telecommunications network, such as SDH (Synchronous Data Hierarchy), where a first node N1 has a first local clock OL1. Said local clock OL1 supplies clock to a transmitter TX1. The first node N1 communicates with a second node N2 by sending a data signal DIN, said node having at its input a phase locked loop PL. Such a phase locked loop PL receives at its input a reference clock signal CKREF generated by a second local clock OL2. The local clock OL1 and local clock OL2 are synchronous by assumption, so that in principle the reference clock signal CKREF should be synchronous with the input data signal DIN, whereas the phase of said signals may be different. Moreover, some mistunes may also occur between said signals. Therefore, the phase locked loop PL will produce a recovered clock signal RCK, synchronous and in phase with the input data signal DIN for correct clocking of the operations of a receiver RX2, so that it is able to decode, by sampling, namely by performing a correct clocking, the data signal DIN which are transmitted according to the local clock OL1.
The phase locked loop PLL for recovering a clock signal is a solution commonly in use.
However, such a solution has some drawbacks due to the difficulty of obtaining high performances by means of the PLL loops, in particular at high frequencies, due to the noise and electric coupling with other circuits. In particular, these difficulties are enhanced in connection with SDH network data transmission.
Moreover, PLL loops appear to be strongly dependent on frequency, so that the use of the same PLL loop at a different frequency is not possible without redesigning the whole ring.
Also, the use of PLL loops notoriously introduces a ‘jitter’, i.e. a frequency distortion, which is reflected in phase changes.
As an alternative to phase locked loop rings, it is known to use delay locked loops also known as DLL loops (Delay Locked Loop).
DLL rings are also based on feedback rings with a delay line receiving an input clock signal and releasing on their output one or more signals which are delayed with respect to the clock signal. Therefore, a phase comparator controls the phase difference with respect to the signal to be tracked and consequently instructs a control logics driving the delay introduced by the delay line.
One problem associated to this type of circuits is that the delay elements of the delay lines practically have considerable deviations from said nominal delay or phase shift value. Consequently, rather high delay values should be used, so that the incidence of said deviation is less important. As a result, the partition that can be operated on the bit period of the input data signal cannot be a very fine one. Moreover, such DLL circuits make extremely difficult to track a strong jitter of input data.